1. Field of the Invention
The present application relates generally to integrated circuits, and more particularly to integrated circuit design and fabrication.
2. Description of the Background Art
In recent years, integrated circuits (ICs) have been increasing in complexity and in the degree of integration with each generation. Integrated circuits generally include multiple patterned conducting, semiconducting and dielectric layers formed on a substrate, such as a silicon wafer, by a combination of photolithographic, etching and deposition techniques. The increased complexity of latest generation of devices require finer and more accurately formed wiring and interconnects or vias. Thus, before each successive layer is formed, the underlying surface or present layer is planarized by, for example, chemical-mechanical planarization (CMP). CMP, which is also known as “chemical-mechanical polishing,” produces a substantially flat surface across the layer provided the layer has a substantially uniform density in a distribution or spacing of elements or features across the surface.
Although planarization can flatten small imperfections relatively well, differences in the size and spacing of various elements in a patterned layer can often yield significant differences in density of the layer, resulting in non-uniform planarization across the surface of the substrate. This is a problem particularly for metal containing wiring and interconnect layers as illustrated in FIG. 1. FIG. 1 schematically shows a side sectional view of a portion of an integrated circuit having metal lines 102 (i.e., 102-1, 102-2, 102-3) and an overlying oxide polished by CMP. In the example of FIG. 1, the non-uniform planarization is in the dashed region 101, in particular between metal lines 102-2 and 102-3. Labels 105 points to the profile of the oxide before the CMP process, while label 104 points to the profile of the oxide after the CMP process.
In the past, the problem of non-uniform planarization has been addressed by adding one or more dummy patterns in regions where a pattern density of the metal lines is below a fixed limit. A dummy pattern includes a plurality of dummy features, such as the so-called “waffles.” Waffles are “dummy features” because although they are formed like metal lines, waffles are not designed to have an electrical function in an integrated circuit. That is, although typical waffles comprise metal, they are not designed to carry electrical current. In contrast, a “metal line” or “metal layer” is designed to function as an interconnect. An example of metal lines and a waffle included in a conventional waffling pattern is shown in FIG. 2. In the example of FIG. 2, a waffle 201 is placed between metal lines 203-1 and 203-2 on the same level of the integrated circuit. Metal lines 203-1 and 203-2 are part of a metal pattern that comprises several metal lines. Metal line 202 is on a level of the integrated circuit that is below metal lines 203 (i.e., 203-1, 203-2), while metal lines 204 (i.e., 204-1, 204-2) are on a metal level that is above metal lines 203. Interlayer dielectrics (ILD) 205 and 206 separate the metal levels.
Typically, the inclusion of waffling patterns has been accomplished automatically using computer aided design (CAD) programs and rather simple algorithms that generate waffles of a predetermined size, shape and spacing across the entire surface of the substrate or layer wherever there is no conflict with elements of the metal pattern. Although successful in producing a substantially planar surface, this technique has not been wholly satisfactory for a number of reasons.
In particular, as circuit geometries decrease and metal thicknesses increase, the waffles have an increasingly large impact on parasitic capacitance and coupling between elements of the metal layer (i.e., between metal lines). Electric fields generated between metal lines 301 and 302 without an intervening waffle are shown in FIG. 3A. FIG. 3B shows coupling between the metal lines 301 and 302 through an intervening, conventionally placed waffle 303. Waffle 303 is electrically floating because it is not designed to carry electrical current. Parasitic capacitance and coupling between metal lines can cause transients that delay signal propagation through them, degrading the performance of the integrated circuit from that for which it was designed. Moreover, as circuit complexity increases, the process of designing and placing the waffles, and of re-checking the design after inclusion of the waffle pattern, consumes increasing amounts of design time and resources.